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| BF 1005 Silicon N-Channel MOSFET Tetrode * For low noise, high gain controlled input stages up to 1GHz * Operating voltage 5V * Integrated stabilized bias network ESD: Electrostatic discharge sensitive device, observe handling precaution! Type BF 1005 Marking Ordering Code Pin Configuration MZs Q62702-F1498 1 = S 2=D Package 3 = G2 4 = G1 SOT-143 Maximum Ratings Parameter Drain-source voltage Continuos drain current Gate 1/gate 2 peak source current Gate 1 (external biasing) Total power dissipation, T S 76 C Storage temperature Channel temperature Symbol Value 8 25 10 3 200 - 55 ...+150 150 V mW C Unit V mA VDS ID I G1/2SM +VG1SE Ptot T stg T ch Thermal Resistance Channel - soldering point Rthchs 370 K/W Note: It is not recommended to apply external DC-voltage on Gate 1 in active mode. Semiconductor Group Semiconductor Group 11 Au 1998-11-01 -25-1998 BF 1005 Electrical Characteristics at TA = 25C, unless otherwise specified. Symbol Values Parameter min. DC characteristics Drain-source breakdown voltage typ. 100 10 1 max. 12 13 50 1.5 - Unit V(BR)DS V (BR)G1SS V (BR)G2SS +I G1SS I G2SS 12 8 8 8 - V I D = 650 A, -V G1S = 4 V, - V G2S = 4 V Gate 1 source breakdown voltage I G1S = 10 mA, VG2S = V DS = 0 Gate 2 source breakdown voltage I G2S = 10 mA, VG1S = 0 V, V DS = 0 V Gate 1 source current A nA mA VG1S = 6 V, V G2S = 0 V Gate 2 source leakage current VG2S = 8 V, V G1S = 0 V, V DS = 0 V Drain current I DSS I DSO VG2S(p) VDS = 5 V, V G1S = 0 , V G2S = 4.5 V Operating current (selfbiased) VDS = 5 V, V G2S = 4.5 V Gate 2-source pinch-off voltage V VDS = 5 V, ID = 100 A AC characteristics Forward transconductance (self biased) g fs Cg1ss Cdss G ps F 800 Gps 40 24 2.1 1.3 19 1.4 50 2.5 - mS pF VDS = 5 V, V G2S = 4.5 V, f = 1 kHz Gate 1-input capacitance (self biased) VDS = 5 V, V G2S = 4 V, f = 1 MHz Output capacitance (self biased) VDS = 5 V, V G2S = 4 V, f = 100 MHz Power gain (self biased) dB VDS = 5 V, V G2S = 4 V, f = 800 MHz Noise figure (self biased) VDS = 5 V, V G2S = 4 V, f = 800 MHz Gain control range (self biased) VDS = 5 V, V G2S = 1 V, f = 800 MHz Semiconductor Group Semiconductor Group 22 Au 1998-11-01 -25-1998 BF 1005 Total power dissipation P tot = f (T S) Drain current ID = f (VG2S) 300 12 mA mW 10 9 P tot 200 8 ID 7 150 6 5 100 4 3 50 2 1 0 0 20 40 60 80 100 120 C 150 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V 5.0 TS VG2S Insertion power gain | S 21 | 2 = f (V G2S) 10 dB Forward transfer admittance | Y 21 | = f (V G2S) 26 mS 0 -5 22 20 | S21 |2 -15 -20 -25 -30 -35 -40 -45 -50 -55 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V |Y21| -10 18 16 14 12 10 8 6 4 2 5.0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V 5.0 VG2S VG2S Semiconductor Group Semiconductor Group 33 Au 1998-11-01 -25-1998 BF 1005 Gate 1 input capacitance Cg1ss = f (V g2s) f = 200MHz Output capacitance C dss = f (V G2) f = 200MHz 3.0 pF 3.0 pF 2.4 2.2 2.4 2.2 Cg1ss 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 V Cdss 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 5.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V 5.0 VG2S VG2S Semiconductor Group Semiconductor Group 44 Au 1998-11-01 -25-1998 |
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